This invention relates to a semiconductor device having an insulated gate field-effect transistor, and particularly relates to an improvement in an operation speed thereof.
Conventionally, especially in an n-channel type MOS transistor, an LDD (lightly doped drain) structure in which an impurity atom concentration near a channel of a drain region is made low by implanting ion into heavily doped source and drain regions after providing side walls (spacers) at a gate electrode is applied in order to have high drain breakdown voltage. In this structure, since the lightly doped drain reduces an electric field near the drain, high reliability in durability to high the drain is obtained. However, in the general MOS transistor with LDD structure, almost part of the lightly doped drain is located outside of the gate electrode, so that the region therein located outside of the gate is pinched off to have high resistivity. This causes degradation in drive current. Further, since a hot carrier is generated below the side walls and is implanted into and held in the side walls, the lightly doped drain is pinched off to have higher resistivity. As a result, the degradation in drive current due to the hot carrier is caused in an earlier stage than a single source/drain structure ("spacer-induced degradation").
As disclosed in IEDM Technical Digest, 1989, p.777 (see FIG. 13), a MOS transistor with LATID (large-angle-tilt implanted drain) structure is proposed as a modified transistor with LDD structure. In detail, the lightly doped source 4 and the lightly doped drain 5 are formed below a near-end part of the gate electrode 3, mainly not below the spacers 6, by two-step wise implant with a tilted angle of 45.degree., instead of a conventional ion implant at an angle approximately in parallel with a normal of the substrate (usually 7.degree. for preventing channeling). Accordingly, the MOS transistor with LATID structure is prevented from having high resistivity caused by the pinch off of the lightly doped drain. Thus, the transistor with LATID structure has much higher drivability and higher reliability than that with LDD structure.
FIGS. 14(a) and (b) show respective results of two-dimensional simulation near the drain in electric field E.sub.// (MV/cm) in a lateral direction, electron concentration Ne (cm.sup.-3) and generation frequency Rg (cm.sup.-3,s.sup.-1) of pairs of hot carriers for the MOS transistor with LATID structure and that with LDD structure. Hatched regions are regions whose hot carrier pair generation frequencies Rg are more than 10.sup.28. The impurity atom concentration of the substrate is about 1.times.10.sup.17 cm.sup.-3. Wherein biassing conditions are as follows: drain voltage Vd=5 V, gate voltage Vg=2 V and substrate voltage Vsub=0 V. At these biassing conditions a drain avalanche hot carrier is generated, which causes the severest degradation of the n-channel type MOS transistor. When the gate voltage Vg is smaller than the drain voltage Vd, the drain region near the gate electrode is depleted, and electric current is deflected around the depletion region. In the MOS transistor with LATID structure, the current is deflected around the depletion and flows in a deeper part, so that the hot carrier is generated at a deeper point. As a result, the generated hot carrier is likely to be scattered and is hard to be implanted into a gate oxide layer. On the other hand, with LDD structure, the depletion region is small and is formed far from a point to which the electric field concentrates. Therefore, the current flows near the surface with less influence of the depletion region, so that the hot carrier is generated near the surface. This is one of the reasons why the MOS transistor with LATID structure has high reliability. With LDD structure, the point which electric field concentrates is located under the side wall to generate "spacer-induced degradation".
In the MOS transistor with LATID structure, however, the lightly doped source and the lightly doped drain extend under the gate electrode, which means that the source and the drain are formed at a shallower part with respect to the surface of the substrate. Therefore, the LATID structure cannot fully display its effect. Moreover, the longer an overlap length Lov between the gate and the drain is, the larger a capacity Cgd between the gate and the drain is, with a result that a circuit operation speed cannot correspond to an increased drivability.
U.S. Pat. No. 4,746,624 discloses a BLDD (buried lightly doped drain) structure (see FIG. 15) and a method of making the same. In the BLDD structure, less hot carrier is implanted into and held in the side wall and the drive current is prevented from degradation in such a manner that in LDD structure a buried drain of a third region whose impurity atom concentration is higher than that of the lightly doped drain and lower than that of the heavily doped drain is provided in the substrate at a portion set-distance deep from the substrate surface so that the portion at which the hot carrier is generated is far from the substrate surface. In the method, the buried drain is shifted back and a fourth region, i.e., a blocking region of n.sup.- (or p or intrinsic semiconductor) which has high resistivity is provided at a boundary of the lightly doped drain and the heavily doped drain in order to decrease a short channel effect generated in BLDD structure (see FIG. 11).
However, in BLDD structure, when the channel length is short accompanied by scaling down the semiconductor device, a punch-through is likely to occur along a route shown by an arrow in broken line in FIG. 16, which means severe short channel effect (refer to the U.S. Patent). Particularly, even when the buried drain is provided so as to overlap under the gate electrode to avoid to have high resistivity due to the pinch-off, the gate/drain capacity of the lightly doped source and the lightly doped drain is large. Consequently, as well as LATID structure, the operation speed is hardly enhanced.
The U.S. Pat. No. 4,746,624 approaches to suppress the short channel effect which is the disadvantage of the BLDD structure. The method therein has complicated steps of forming a gate electrode, forming lightly doped source and drain, forming a first side wall, forming a blocking region B by counter doping, forming a second side wall and forming heavily doped source and drain. Further, the boundary of the lightly doped drain and the heavily doped drain is located under the side wall, so that the blocking region B is not formed under the gate electrode. Therefore, since the current flows at a deeper part under the side wall which the gate voltage hardly affects, further lowering of the current drivability may be caused with less improvement in the operation speed.
With the above LDD, LATID and BLDD structures, the gate/drain capacity cannot be reduced and improvement in the operation speed of the semiconductor device is limited because the effective impurity atom concentration is made increased from the inside of the substrate toward the surface thereof at the surface of lightly doped source and drain regions. This invention is made in view of this disadvantage and has its object of enhancing the reliability and contemplating the high speed operation of the transistor without degradation of short channel effect by making the effective impurity atom concentration lowered from the inside of the substrate toward the surface thereof in lightly doped source and drain regions in a transistor with LATID structure.